This invention relates to memory decoders of semiconductor memories.
In memory systems, non-volatile memories may include subword line decoders which generate a subword line (SWL) output to perform read, erase, or program functions on a portion of the memory. Subword line decoders route different voltages along the subword line to perform the different read, erase or program functions.
In memory systems, there may be multiple subword line decoders per bank of memory. One example of a memory using subword line decoders with subword lines is illustrated in commonly assigned U.S. Pat. No. 5,506,816, issued on Apr. 9, 1996, entitled xe2x80x9cMemory Cell Array Having Compact Word Line Arrangement,xe2x80x9d the disclosure of which is expressly incorporated herein by reference in its entirety.
FIG. 1 shows one example of a subword line decoder 10 having a subword line (SWL) 12. The inputs to the subword line decoder are the P-well line, the source line, the global word line (GWL) 14, the block select line (BKS) and its complement (BKSB). Based on the values of these input signals, the subword line decoder 10 produces an output signal 12 shown as the subword line, which may be passed to the gate of a memory cell (not shown) to perform a read, erase or program operation of the memory cell.
The subword line decoder 10 passes onto the subword line 12 both the full power levels (i.e., +5 volts), as well as other high voltage signals (i.e., xe2x88x925 volts). A high voltage signal, in this context, includes voltages which are outside of the normal power supply range of the integrated circuit. For example, in a circuit which operates on logic levels of zero to +5 volts, a high voltage signal would include a negative voltage reference of xe2x88x925 volts, referred to herein as the VNEG signal. While not shown in these figures, it is assumed that the high voltage signal VNEG is generated by a high voltage generating circuit capable of creating a high voltage signal such as xe2x88x925 volts.
In one example, the VNEG signal of 0 to xe2x88x925 volts is a high voltage signal used to program or erase the contents of a memory cell. In one example, the VNEG signal is at ground during standby and read operations, and the VNEG signal is pumped or forced to a high voltage negative potential, such as xe2x88x925 volts, during an erase or program operation in the non-volatile memory.
In FIG. 1, the transistor P1 is a pass transistor that, when a voltage of +5 volts is present on the global word line 14 and transistor P1 is on, transistor P1 passes that voltage to the subword line 12. When the global word line 14 is at xe2x88x925 volts, transistor N1 acts as a pass transistor which passes the xe2x88x925 volts of the global word line 14 to the subword line 12. Transistors N2 and P2 provide a deselect path which connects the source line to the subword line 12.
As recognized by the present inventor, in the circuit of FIG. 1 it is possible that the voltages between the gate and the source of the transistors is a high voltage such as +10 volts, which may over the long term degrade the performance of the transistors. For instance, to turn transistors P1 and N1 on (so that the value of the global word line 14 can be passed to the subword line 12) while disabling transistors P2 and N2, the block select line BKS is driven high (i.e., 5 volts) and the BKSB line is low (i.e., xe2x88x925 volts for an erase and program operation). If the global word line 14 is also at +5 volts during a program operation, then the transistor P1 has a 10 volt bias between its gate and sourcexe2x80x94such a high gate to source voltage across transistor P1 may degrade the transistor over time. Similarly, if the global word line 14 is at xe2x88x925 volts for an erase operation, then transistor N1 has a 10 volt bias between its gate and source, which may degrade transistor N1 over time.
As recognized by the present inventor, what is needed is a subword line decoder which can pass signals of read, erase and program operations without subjecting the transistors of the subword line decoder to stresses resulting from the application of high bias voltages to the transistors.
It is against this background that various embodiments of the present invention were developed.
According to one broad aspect of one embodiment of the present invention, disclosed herein is a subword decoder circuit for generating an output signal, such as a subword line signal, to one or more memory cells of a memory. In one embodiment, the circuit includes four transistors each with a separate select line.
In one example, a first switch is provided and has an input coupled with a global word line input signal; a second switch has an input coupled with the output of the first switch at an output node; a third switch has an input coupled with the global word line input signal and the output of the third switch being coupled with the output of the first switch at the output node; and a fourth switch having an input coupled with the output of the third switch at the output node and the output of the fourth switch is coupled with the output of the second switch. In one embodiment, a first block select line is coupled with the control of said first switch; a second block select line is coupled with the control of the fourth switch. The second block select line may be a complement of the first block select line in one example. A third block select line is coupled with the control of the second switch, and a fourth block select line is coupled with the control of the third switch. The fourth block select line may be a complement of the third block select line.
By providing separate block select line to control the switches, the voltage across the switches is reduced during instances when a high voltage signal is being passed from the global word line to the subword line, or from the source line to the subword line.
In another embodiment, the first switch and the fourth switched can be p-channel transistors. Each p-channel transistor may be formed using a stack of three p-channel transistors, so as to improve the characteristics of the first and fourth switches.
The features, utilities and advantages of various embodiments of the invention will be apparent from the following more particular description of embodiments of the invention as illustrated in the accompanying drawings.